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编辑文件 .cnb.yml

.vscode
Course_Project_1
Course_Project_2
commit
.cnb.yml
.gitignore
Debug.md
Mars4_5.jar
README.md
grader.yml
数字逻辑大作业说明文档-20251030.pdf

Verilog Course Project

This is a digital logic design course project based on Verilog, primarily implementing signed comparators and other digital circuit modules.

Project Structure

Course Project 1/
├── source/                  # Source code directory
│   └── signed_compare_comb.v  # Signed comparator
├── testbench/              # Test files directory
│   ├── tb_signed_comparator.v  # Comparator testbench
│   ├── tb_signed_merge_sort4.v
│   └── tb_signed_sort4.v
└── README.md              # This file

Common Verilog Development Commands

1. Compiling Verilog Files

Using Icarus Verilog compiler:

# Basic compilation syntax
iverilog -o output_file source1.v source2.v ...

# Example: Compile comparator module and testbench
iverilog -o test_signed_compare testbench/tb_signed_comparator.v source/signed_compare_comb.v

# Compile single module file (syntax check)
iverilog source/signed_compare_comb.v

2. Running Simulations

Execute compiled simulation files:

# Basic run syntax
vvp compiled_file_name

# Example: Run comparator test
vvp test_signed_compare

# Compile and run directly
iverilog -o test_signed_compare testbench/tb_signed_comparator.v source/signed_compare_comb.v && vvp test_signed_compare

3. Output Processing Commands

View and process simulation outputs:

# View complete output
vvp test_signed_compare

# View first 50 lines
vvp test_signed_compare | head -50

# View last 5 lines
vvp test_signed_compare | tail -5

# Find error messages
vvp test_signed_compare | grep "ERROR"

# Count number of errors
vvp test_signed_compare | grep "ERROR" | wc -l

# Save output to file
vvp test_signed_compare > simulation_output.txt

# Show only passes and failures
vvp test_signed_compare | grep -E "(PASS|ERROR)"

4. Project Navigation Commands

Quick navigation in project directory:

# Enter project directory
cd "/workspace/Course Project 1"

# View project structure
tree .
# or
find . -name "*.v" -type f

# View all Verilog files
ls -la source/*.v testbench/*.v

# Search content in files
grep -r "module" source/ testbench/
grep -r "parameter" source/
grep -r "assign" source/

5. Common Development Workflow

Complete development and testing workflow:

# 1. Enter project directory
cd "/workspace/Course Project 1"

# 2. Check code syntax
iverilog source/your_module.v

# 3. Compile and run tests
iverilog -o test_module testbench/tb_your_module.v source/your_module.v
vvp test_module

# 4. View test results
vvp test_module | grep -E "(PASS|ERROR)" | tail -10

# 5. If there are errors, view detailed error information
vvp test_module | grep "ERROR" -A 2 -B 2

6. Debugging

# View detailed compilation information
iverilog -v source/your_module.v

# Generate detailed simulation report
vvp -v test_module

# View specific pattern messages
vvp test_module | grep -E "(num_a=.*num_b=.*ERROR|PASS.*)"

# Count number of test cases
vvp test_module | wc -l